Flix Format neugeneriert

fft_inst.tie

@@ -147,9 +147,10 @@ operation FFT_shift_check {in AR fr, in AR fi, out BR needs_shift} {}
 	assign needs_shift = jc1[0] | jc2[0] | jc3[4] | jc4[4];
 } 
 
+
 operation FFT_bit_reverse {inout AR m, out AR mr, in AR mm} {}
 {
-	wire [15:0] x = TIEadd(m, 0, 1'b1);
+	wire [15:0] x = TIEadd(m, 1'b0, 1'b1);
 	assign mr = {
 		TIEmux(mm[2:0], 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, x[0]),
 		TIEmux(mm[2:0], 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, x[0], x[1]),
@@ -209,11 +210,96 @@ operation FFT_calc {inout FFT_reg data, in AR wr, in AR wi, in AR shift} {}
 	};
 }
 
-format flix64_0 64 { flix64_0_slot0, flix64_0_slot1 }
+////////////////////////////////////////////////////////////////////////////
+//
+// Generated by XPRES v4.0.4
+// Sat Mar 07 17:29:10 2015
+//
+// Register Files
+//   AR (a): 16 entries, 32 bits per entry, ports 3r / 2w
+//   vec (v): 16 entries, 160 bits per entry, ports 3r / 1w
+//   valign (u): 4 entries, 128 bits per entry, ports 2r / 1w
+//   sel (s): 8 entries, 32 bits per entry, ports 2r / 1w
+//   FFT_reg (fftv): 2 entries, 64 bits per entry, ports 1r / 1w
+// 
+// FLIX Formats
+//   x24: size 24 bits, 1 slot
+//     slot Inst: size 24 bits
+//       opcodes { }
+//   x64: size 64 bits, 3 slots
+//     slot vsLDST: size 24 bits
+//       opcodes { }
+//     slot vsMAC: size 18 bits
+//       opcodes { }
+//     slot vsALU: size 18 bits
+//       opcodes { }
+//   flix64_0: size 64 bits, 2 slots
+//     slot flix64_0_slot0: size 24 bits
+//       opcodes { L16SI NOP ld.FFT_reg mv.FFT_reg st.FFT_reg }
+//     slot flix64_0_slot1: size 10 bits
+//       opcodes { MOV.N NOP }
+// 
+// This TIE requires the following configuration settings:
+//
+//	 Required Endian: Little
+//	 Required Instruction Width: 64 bits
+//	 Minimum Data-Memory Width: 128 bits
+//	 Required Load/Store Units: 1
+//	 Requires Byte Enables: Yes
+//	 Requires Booleans: No
+//	 Pipeline Length: 5 stages
+//
+// This TIE was generated on a processor configuration with the
+// following ISA instruction options enabled:
+//
+//	 CLAMPS
+//	 MUL16
+//	 NSA/NSAU
+//	 MIN/MAX and MINU/MAXU
+//	 Sign Extend to 32 Bits
+//	 Enable Density Instructions
+//	 Enable Boolean Registers
+//	 Zero Overhead Loop Instructions
+//	 Vectra LX DSP Coprocessor Instruction Family
+//
+////////////////////////////////////////////////////////////////////////////
 
+
+//--------------------------------------------------------------------------
+//
+// Immediate Ranges
+//
+//--------------------------------------------------------------------------
+
+immediate_range st.FFT_reg_immed2 -32 24 8
+immediate_range ld.FFT_reg_immed2 -32 24 8
+
+//--------------------------------------------------------------------------
+//
+// FLIX Formats and Slots
+//
+// flix64_0, format width 64 bits, 2 slots
+// 
+//--------------------------------------------------------------------------
+
+
+format flix64_0 64 { flix64_0_slot0, flix64_0_slot1, flix64_0_slot2 }
+
+slot_opcodes Inst {
+	 FFT_bit_reverse, FFT_calc, FFT_shift_check, FFT_twiddle, ld.FFT_reg,
+	 mv.FFT_reg, st.FFT_reg }
 slot_opcodes flix64_0_slot0 {
-	 ADD, ADDI, BGEU, BLTU, L16SI, L32I, MOVNEZ, NEG, NOP, S16I, SEXT, SRAI, SUB, FFT_twiddle,
-	 ld.FFT_reg, mv.FFT_reg, st.FFT_reg, FFT_calc, FFT_shift_check, FFT_bit_reverse}
+	 ADD, BEQZ, BGEU, BLTU, BNEZ, L16SI, MOV.N, NOP, S16I, SEXT, SUB }
 slot_opcodes flix64_0_slot1 {
-	 ADD, ADDI, ADDX2, xt_widebranch18, BEQZ, BGE, BLT, BNEZ, FFT_twiddle, J,
-	 MOV.N, NOP, SEXT, SRAI, SUB, FFT_calc, FFT_shift_check, FFT_bit_reverse}
+	 ADD, ADDX2, MOV.N, MOVNEZ, NEG, NOP }
+slot_opcodes flix64_0_slot2 {
+	 ADD, L16SI, NOP, S16I, SUB }
+
+
+//--------------------------------------------------------------------------
+//
+// Ctypes
+//
+//--------------------------------------------------------------------------
+
+ctype FFT_reg 64 64 FFT_reg default