Merge remote-tracking branch 'github/simd'
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608a750738
@ -126,6 +126,7 @@ int fix_fft_org(fixed fr[], fixed fi[], int m, int inverse)
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wr >>= 1;
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wi >>= 1;
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}
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for(i=m; i<n; i+=istep)
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{
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@ -148,6 +149,7 @@ int fix_fft_org(fixed fr[], fixed fi[], int m, int inverse)
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fi[i] = qi + ti;
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}
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}
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--k;
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l = istep;
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}
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22
fft.c
22
fft.c
@ -37,6 +37,14 @@
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#include <stdio.h>
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#define FFT_COMBINED_STORE(_fr, _fi, _i, _simd_r, _simd_i) \
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asm ("{" "\n" \
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" fft_simd_store %1, %0, %2" "\n" \
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" nop" "\n" \
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" fft_simd_store %3, %0, %4" "\n" \
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"}" \
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:: "r" (_i), "r" (_fr), "r" (_simd_r), "r" (_fi), "r" (_simd_i));
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/*
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* fix_fft() - perform fast Fourier transform.
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*
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@ -112,8 +120,21 @@ int fix_fft(fixed fr[], fixed fi[], int m, int inverse)
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istep = l << 1; //step width of current butterfly
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FFT_REG reg;
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FFT_REG_SIMD simd_r, simd_i;
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fixed *reg_s = ((fixed*) ®);
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if(l == 1)
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{
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for(i=0; i<n; i+=8)
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{
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simd_r = FFT_simd_load(fr, i);
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simd_i = FFT_simd_load(fi, i);
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FFT_SIMD_FIRST(simd_r, simd_i, (xtbool) shift);
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FFT_COMBINED_STORE(fr, fi, i, simd_r, simd_i);
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}
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}
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else
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{
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for(m=0; m<n; m+=istep)
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{
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for(i=m; i<m+l; ++i)
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@ -133,6 +154,7 @@ int fix_fft(fixed fr[], fixed fi[], int m, int inverse)
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fi[j] = reg_s[0];
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}
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}
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}
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--k;
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l = istep;
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}
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130
fft_inst.tie
130
fft_inst.tie
@ -132,6 +132,62 @@ table SIN_WAVE 16 1024 {
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regfile FFT_REG 64 2 fftv
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regfile FFT_REG_SIMD 128 2 fftsv
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function [31:0] FFT_VAR_SHIFT([31:0] data, [3:0] sh)
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{
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assign FFT_VAR_SHIFT = TIEmux(sh,
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data[31:0],
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{data[30:0], 1'b0},
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{data[29:0], 2'b0},
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{data[28:0], 3'b0},
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{data[27:0], 4'b0},
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{data[26:0], 5'b0},
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{data[25:0], 6'b0},
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{data[24:0], 7'b0},
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{data[23:0], 8'b0},
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{data[22:0], 9'b0},
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{data[21:0], 10'b0},
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{data[20:0], 11'b0},
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{data[19:0], 12'b0},
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{data[18:0], 13'b0},
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{data[17:0], 14'b0},
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{data[16:0], 15'b0}
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);
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}
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operation FFT_SIMD_LOAD {in AR *base, in AR offset, out FFT_REG_SIMD data} {out VAddr, in MemDataIn128}
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{
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assign VAddr = TIEadd(base, {offset[30:0], 1'b0}, 1'b0);
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wire [15:0] o1 = MemDataIn128[15:0];
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wire [15:0] o2 = MemDataIn128[31:16];
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wire [15:0] o3 = MemDataIn128[47:32];
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wire [15:0] o4 = MemDataIn128[63:48];
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wire [15:0] o5 = MemDataIn128[79:64];
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wire [15:0] o6 = MemDataIn128[95:80];
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wire [15:0] o7 = MemDataIn128[111:96];
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wire [15:0] o8 = MemDataIn128[127:112];
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assign data = {o1, o2, o3, o4, o5, o6, o7, o8 };
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}
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operation FFT_SIMD_STORE {in AR *base, in AR offset, in FFT_REG_SIMD data} {out VAddr, out MemDataOut128}
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{
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assign VAddr = TIEadd(base, {offset[30:0], 1'b0}, 1'b0);
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wire [15:0] o1 = data[15:0];
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wire [15:0] o2 = data[31:16];
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wire [15:0] o3 = data[47:32];
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wire [15:0] o4 = data[63:48];
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wire [15:0] o5 = data[79:64];
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wire [15:0] o6 = data[95:80];
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wire [15:0] o7 = data[111:96];
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wire [15:0] o8 = data[127:112];
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assign MemDataOut128 = {o1, o2, o3, o4, o5, o6, o7, o8 };
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}
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operation FFT_SHIFT_CHECK {in AR *base, in AR offset, out AR needs_shift} {out VAddr, in MemDataIn128}
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{
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assign VAddr = TIEadd(base, offset[31:1], 1'b0);
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@ -243,59 +299,21 @@ operation FFT_CALC {inout FFT_REG data, in AR i, in BR shift, in BR inverse} {}
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assign data = FFT_BUTTERFLY(data, wr, wi, shift);
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}
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////////////////////////////////////////////////////////////////////////////
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//
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// Generated by XPRES v4.0.4
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// Sat Mar 07 17:29:10 2015
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//
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// Register Files
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// AR (a): 16 entries, 32 bits per entry, ports 3r / 2w
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// vec (v): 16 entries, 160 bits per entry, ports 3r / 1w
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// valign (u): 4 entries, 128 bits per entry, ports 2r / 1w
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// sel (s): 8 entries, 32 bits per entry, ports 2r / 1w
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// FFT_reg (fftv): 2 entries, 64 bits per entry, ports 1r / 1w
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//
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// FLIX Formats
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// x24: size 24 bits, 1 slot
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// slot Inst: size 24 bits
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// opcodes { }
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// x64: size 64 bits, 3 slots
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// slot vsLDST: size 24 bits
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// opcodes { }
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// slot vsMAC: size 18 bits
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// opcodes { }
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// slot vsALU: size 18 bits
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// opcodes { }
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// flix64_0: size 64 bits, 2 slots
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// slot flix64_0_slot0: size 24 bits
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// opcodes { L16SI NOP ld.FFT_reg mv.FFT_reg st.FFT_reg }
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// slot flix64_0_slot1: size 10 bits
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// opcodes { MOV.N NOP }
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//
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// This TIE requires the following configuration settings:
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//
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// Required Endian: Little
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// Required Instruction Width: 64 bits
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// Minimum Data-Memory Width: 128 bits
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// Required Load/Store Units: 1
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// Requires Byte Enables: Yes
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// Requires Booleans: No
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// Pipeline Length: 5 stages
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//
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// This TIE was generated on a processor configuration with the
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// following ISA instruction options enabled:
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//
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// CLAMPS
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// MUL16
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// NSA/NSAU
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// MIN/MAX and MINU/MAXU
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// Sign Extend to 32 Bits
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// Enable Density Instructions
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// Enable Boolean Registers
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// Zero Overhead Loop Instructions
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// Vectra LX DSP Coprocessor Instruction Family
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//
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////////////////////////////////////////////////////////////////////////////
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// 4 butterflies at once
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operation FFT_SIMD_FIRST {inout FFT_REG_SIMD fr, inout FFT_REG_SIMD fi, in BR shift} {}
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{
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wire [15:0] wr = TIEmux(shift, 16'h7fff, 16'h3fff);
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wire [15:0] wi = 16'b0;
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wire [63:0] res1 = FFT_butterfly({fr[127:96], fi[127:96]}, wr, wi, shift);
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wire [63:0] res2 = FFT_butterfly({fr[95:64], fi[95:64]}, wr, wi, shift);
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wire [63:0] res3 = FFT_butterfly({fr[63:32], fi[63:32]}, wr, wi, shift);
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wire [63:0] res4 = FFT_butterfly({fr[31:0], fi[31:0]}, wr, wi, shift);
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assign fr = { res1[63:32], res2[63:32], res3[63:32], res4[63:32] };
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assign fi = { res1[31:0], res2[31:0], res3[31:0], res4[31:0] };
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}
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//--------------------------------------------------------------------------
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@ -314,10 +332,9 @@ immediate_range LD.FFT_REG_immed2 -32 24 8
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// flix64_0, format width 64 bits, 2 slots
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format flix64_0 64 { flix64_0_slot0, flix64_0_slot1, flix64_0_slot2 }
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//Full slots:
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slot_opcodes flix64_0_slot0 { MOVI, J, ADDX2, L16SI, S16I, FFT_BIT_REVERSE, S32I, L32I, FFT_SHIFT_CHECK, OR, NOP, ADD, FFT_CALC }
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slot_opcodes flix64_0_slot0 { MOVI, J, ADDX2, L16SI, S16I, FFT_BIT_REVERSE, S32I, L32I, FFT_SHIFT_CHECK, OR, NOP, ADD, FFT_CALC, FFT_SIMD_LOAD, FFT_SIMD_STORE }
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slot_opcodes flix64_0_slot1 { SSL, SLL, MOVI, ADDX2, NOP, ADDI.N, ANDBC, ADD, MOV.N, J }
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slot_opcodes flix64_0_slot2 { S32I, ADDI.N, L32I, L16SI, ADDX2, NOP, FFT_SHIFT_CHECK, J, MOVI, SSL, MOV.N, S16I }
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slot_opcodes flix64_0_slot2 { S32I, ADDI.N, L32I, L16SI, ADDX2, NOP, FFT_SHIFT_CHECK, J, MOVI, SSL, MOV.N, S16I, FFT_SIMD_LOAD, FFT_SIMD_STORE }
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//--------------------------------------------------------------------------
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@ -328,3 +345,4 @@ slot_opcodes flix64_0_slot2 { S32I, ADDI.N, L32I, L16SI, ADDX2, NOP, FFT_SHIFT_C
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//--------------------------------------------------------------------------
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ctype FFT_REG 64 64 FFT_REG default
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ctype FFT_REG_SIMD 128 128 FFT_REG_SIMD default
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