heron_sqrt/Makefile

C99?=c99
PROJECT_ROOT=/home2/vlsi13/joth13/ICPRO/ice/heron/units/heron
TB_ROOT=$(PROJECT_ROOT)/df2/heron_top_tb_run1

all: bericht check fsm_tb

bericht:
	cd bericht && make

check: sqrt
	./sqrt

sqrt: c/sqrt.c
	$(C99) -lm -o sqrt c/sqrt.c

fsm: verilog/heron_fsm.vcd
	gtkwave verilog/heron_fsm.vcd

ctrl: verilog/heron_ctrl.vcd
	gtkwave verilog/heron_ctrl.vcd

fsm_tb: verilog/heron_fsm.vcd
ctrl_tb: verilog/heron_ctrl.vcd

%.vcd : %.vvp
	vvp $<

%.vvp: %_tb.v %.v
	iverilog -o $@ -Iverilog verilog/heron_{fsm,ctrl}.v

VERILOG_FILES=${shell find . -name verilog.v -type f}

sync:
	cd cadence; rsync --relative --verbose -e ssh $(VERILOG_FILES:./cadence/%=%) eeets2:/home2/vlsi13/joth13/ICPRO/ice/heron/units/heron/cdslib/heron/

testbench:
	ssh eeets2 $(PROJECT_ROOT)/df2/run-testbench.sh
	rsync -av --inplace -avHz -e ssh eeets2:$(TB_ROOT)/heron_top_tb.vcd .
	gtkwave heron_top_tb.gtkw