From 162bb47d24bc9d4fabdd5fa9afbae7c813dc762f Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?J=C3=B6rg=20Thalheim?= <joerg@higgsboson.tk>
Date: Wed, 14 Jan 2015 10:35:53 +0100
Subject: [PATCH] display ram after run

---
 cadence/heron_top_tb/functional/verilog.v | 40 +++++++++++++++++++----
 1 file changed, 33 insertions(+), 7 deletions(-)

diff --git a/cadence/heron_top_tb/functional/verilog.v b/cadence/heron_top_tb/functional/verilog.v
index 87d6dcc..5fd0681 100644
--- a/cadence/heron_top_tb/functional/verilog.v
+++ b/cadence/heron_top_tb/functional/verilog.v
@@ -5,6 +5,7 @@ module heron_top_tb();
 `define ASSERT_STATE(state) `ASSERT((fsm_state == state), "not expected state")
 
 parameter CYCLE = 50;
+parameter COMMA = 8;
 
 wire  [31:0] edb;
 wire  [31:0] eab;
@@ -22,15 +23,34 @@ always #(CYCLE/2) clk = ~clk;
 
 reg [31:0] ram [0:1023];
 
-wire ram0;
-wire ram1;
-wire ram2;
+wire [31:0] ram0;
+wire [31:0] ram1;
+wire [31:0] ram2;
+wire [31:0] ram3;
+wire [31:0] ram4;
 assign ram0 = ram[0];
 assign ram1 = ram[1];
 assign ram2 = ram[2];
+assign ram3 = ram[3];
+assign ram4 = ram[4];
 
 assign edb = ram_rd_en ? ram[eab[9:0]] : 32'bz;
 
+task displayRam;
+  reg [15:0] j;
+  reg [32:0] after_comma;
+  begin
+    for (j = 1; j <= ram[0]; j = j + 1) begin
+      // display fixed point as decimal
+      after_comma = ((ram[j][COMMA]     * 10000) >> 1) +
+                    ((ram[j][COMMA - 1] * 10000) >> 2) +
+                    ((ram[j][COMMA - 2] * 10000) >> 3) +
+                    ((ram[j][COMMA - 3] * 10000) >> 4);
+      $display("ram[%d] = %d.%d (0x%h)", j, ram[j] >> COMMA, after_comma, ram[j]);
+    end
+  end
+endtask
+
 always @ (posedge clk) begin
   if (ram_wr_en) begin
     ram[eab[9:0]] <= edb;
@@ -52,17 +72,21 @@ initial begin
   $dumpfile("heron_top_tb.vcd");
   $dumpvars;
 
-  ram[0] = 3;
-  ram[3] = 4;
+  ram[0] = 4;
+  ram[4] = 16 << COMMA;
+  ram[3] = 4 << COMMA;
 
-  ram[2] = 0;
-  ram[1] = 1;
+  ram[2] = 0 << COMMA;
+  ram[1] = 1 << COMMA;
 end
 
 initial begin
   `ASSERT_STATE(`IDLE)
   #(5*CYCLE)
   load = 1;
+  reset = 1'b1;
+  #(CYCLE)
+  reset = 1'b0;
   #(CYCLE)
   load = 0;
   // load mem[0] -> number of operands
@@ -115,11 +139,13 @@ initial begin
   for (i = 0; i < 1000; i = i + 1) begin
     if (ready != 0) begin
       $display("%c[32mSUCCESS: heron_top_tb tests bench finished;%c[0m", 27, 27);
+      displayRam();
       $finish;
     end
     #(CYCLE) ;
   end
   $display("%c[31mFAILED: heron_top_tb tests timeout!%c[0m", 27, 27);
+  displayRam();
   $finish(1);
 end
 endmodule