diff --git a/Makefile b/Makefile
index 29f6f5a..4e0719e 100644
--- a/Makefile
+++ b/Makefile
@@ -1,4 +1,6 @@
 C99?=c99
+PROJECT_ROOT=/home2/vlsi13/joth13/ICPRO/ice/heron/units/heron
+TB_ROOT=$(PROJECT_ROOT)/df2/heron_top_tb_run1
 
 all: bericht check fsm_tb
 
@@ -26,5 +28,12 @@ ctrl_tb: verilog/heron_ctrl.vcd
 %.vvp: %_tb.v %.v
 	iverilog -o $@ -Iverilog verilog/heron_{fsm,ctrl}.v
 
+VERILOG_FILES=${shell find . -name verilog.v -type f}
+
 sync:
-	rsync -av --inplace --rsync-path=~/rsync-3.1.0/rsync -avHz -e ssh verilog/ eeets2:verilog
+	cd cadence; rsync --relative --verbose --rsync-path=~/rsync-3.1.0/rsync -e ssh $(VERILOG_FILES:./cadence/%=%) eeets2:/home2/vlsi13/joth13/ICPRO/ice/heron/units/heron/cdslib/heron/
+
+testbench:
+	ssh eeets2 $(PROJECT_ROOT)/df2/run-testbench.sh
+	rsync -av --inplace --rsync-path=~/rsync-3.1.0/rsync -avHz -e ssh eeets2:$(TB_ROOT)/heron_top_tb.vcd .
+	gtkwave heron_top_tb.gtkw