diff --git a/cadence/heron_ctrl/functional/verilog.v b/cadence/heron_ctrl/functional/verilog.v
index 76ad040..d9cf877 100644
--- a/cadence/heron_ctrl/functional/verilog.v
+++ b/cadence/heron_ctrl/functional/verilog.v
@@ -2,7 +2,6 @@
 
 module heron_ctrl(
   ctrl_bus,
-  // rest
   state,
   ready,
   ram_rd_en,
@@ -14,8 +13,13 @@ module heron_ctrl(
   parameter MINUS = 1'b1;
 
   input [3:0] state;
+
   output ready;
+  reg ready = OFF;
+
   output ram_rd_en, ram_wr_en;
+  reg ram_rd_en = OFF;
+  reg ram_wr_en = OFF;
 
   output [22:0] ctrl_bus;
   `define CTRL_WIRE(name,port) \
@@ -24,9 +28,6 @@ module heron_ctrl(
   `include "heron_ctrl_wires.v"
   `undef CTRL_WIRE
 
-  reg ready = OFF;
-  reg ram_rd_en = OFF;
-  reg ram_wr_en = OFF;
 
   always @(state) begin
     ready = OFF;
@@ -42,41 +43,49 @@ module heron_ctrl(
         ready = ON;
       end
       `LD_N_1: begin
+        ram_rd_en = ON;
+
         k0_to_a = ON;
         a_to_eab = ON;
+
         edb_to_din = ON;
-        ram_rd_en = ON;
       end
       `LD_N_2: begin
-        din_to_a = ON;
-        k0_to_b = ON;
         alu_set_z = ON;
+
+        din_to_a = ON;
+
+        k0_to_b = ON;
       end
       `I_GT_ZERO: begin
         alu_res_to_a = ON;
         a_to_i = ON;
       end
       `LD_S_1: begin
-        i_to_a = ON;
-        edb_to_din = ON;
-        a_to_eab = ON;
         ram_rd_en = ON;
+
+        i_to_a = ON;
+        a_to_eab = ON;
+
+        edb_to_din = ON;
       end
       `LD_S_2: begin
-        din_to_a = ON;
-        a_to_s = ON;
-        k1_to_b = ON;
         alu_mode = MINUS;
         alu_set_s = ON;
         alu_set_z = ON;
+
+        din_to_a = ON;
+        a_to_s = ON;
+
+        k1_to_b = ON;
       end
       `S_GT_ONE:; // noop
       `X_1: begin
         s_to_a_shift_1 = ON;
-        s_to_b = ON;
-
         a_to_old_x = ON;
         a_to_x = ON;
+
+        s_to_b = ON;
       end
       `DIV_1: begin
         x_to_a = ON;
@@ -104,14 +113,20 @@ module heron_ctrl(
         a_to_old_x = ON;
       end
       `STORE_X: begin
-        x_to_b_shifted = ON;
         ram_wr_en = ON;
+
+        i_to_a = ON;
+        a_to_eab = ON;
+
+        x_to_b_shifted = ON;
       end
       `DEC_I: begin
-        i_to_a = ON;
-        k1_to_b = ON;
         alu_mode = MINUS;
         alu_set_z = ON;
+
+        i_to_a = ON;
+
+        k1_to_b = ON;
       end
     endcase
   end