From 861d93d2fab81e6f234d3d8e561a909a626e9201 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?J=C3=B6rg=20Thalheim?= Date: Wed, 14 Jan 2015 10:43:13 +0100 Subject: [PATCH] ctrl_wires: add x_to_a_shift_1 signal --- cadence/heron_ctrl_wires/functional/verilog.v | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/cadence/heron_ctrl_wires/functional/verilog.v b/cadence/heron_ctrl_wires/functional/verilog.v index 97beaa3..30eac9a 100644 --- a/cadence/heron_ctrl_wires/functional/verilog.v +++ b/cadence/heron_ctrl_wires/functional/verilog.v @@ -21,13 +21,14 @@ module heron_ctrl_wires ( s_to_a_shift_1, s_to_b, x_to_a, + x_to_a_shift_1, x_to_b_shifted ); input [22:0] ctrl_bus; `define CTRL_WIRE(name,port) \ output name; \ - assign name = ctrl_bus[port]; - `include "heron_ctrl_wires.v" + assign name = ctrl_bus[port]; + `include "heron_ctrl_wires.v" `undef CTRL_WIRE endmodule