196 lines
3.4 KiB
Verilog
196 lines
3.4 KiB
Verilog
`include "heron_states.v"
|
|
|
|
module heron_ctrl(
|
|
// data path
|
|
a_to_eab,
|
|
a_to_i,
|
|
a_to_old_x,
|
|
a_to_s,
|
|
a_to_x,
|
|
alu_mode,
|
|
alu_res_to_a,
|
|
alu_set_c,
|
|
alu_set_s,
|
|
alu_set_z,
|
|
din_to_a,
|
|
div_to_b_shift_1,
|
|
edb_to_din,
|
|
i_to_a,
|
|
k0_to_a,
|
|
k1_to_b,
|
|
old_x_to_b,
|
|
s_to_a_shift_1,
|
|
s_to_b,
|
|
x_to_a,
|
|
x_to_b_shifted,
|
|
// rest
|
|
state,
|
|
ready,
|
|
ram_rd_en,
|
|
ram_wr_en);
|
|
|
|
// readability
|
|
parameter ON = 1'b1;
|
|
parameter OFF = 1'b0;
|
|
parameter MINUS = 1'b1;
|
|
parameter PLUS = 1'b0;
|
|
|
|
// data path
|
|
output a_to_eab;
|
|
output a_to_i;
|
|
output a_to_old_x;
|
|
output a_to_s;
|
|
output a_to_x;
|
|
output alu_mode;
|
|
output alu_res_to_a;
|
|
output alu_set_c;
|
|
output alu_set_s;
|
|
output alu_set_z;
|
|
output din_to_a;
|
|
output div_to_b_shift_1;
|
|
output edb_to_din;
|
|
output i_to_a;
|
|
output k0_to_a;
|
|
output k1_to_b;
|
|
output old_x_to_b;
|
|
output s_to_a_shift_1;
|
|
output s_to_b;
|
|
output x_to_a;
|
|
output x_to_b_shifted;
|
|
|
|
input [3:0] state;
|
|
output ready;
|
|
output ram_rd_en;
|
|
output ram_wr_en;
|
|
|
|
// data path
|
|
reg a_to_eab;
|
|
reg a_to_i;
|
|
reg a_to_old_x;
|
|
reg a_to_s;
|
|
reg a_to_x;
|
|
reg alu_mode;
|
|
reg alu_res_to_a;
|
|
reg alu_set_c;
|
|
reg alu_set_s;
|
|
reg alu_set_z;
|
|
reg din_to_a;
|
|
reg div_to_b_shift_1;
|
|
reg edb_to_din;
|
|
reg i_to_a;
|
|
reg k0_to_a;
|
|
reg k1_to_b;
|
|
reg old_x_to_b;
|
|
reg rom_rd_en;
|
|
reg s_to_a_shift_1;
|
|
reg s_to_b;
|
|
reg x_to_a;
|
|
reg x_to_b_shifted;
|
|
|
|
reg ready;
|
|
reg ram_rd_en;
|
|
reg ram_wr_en;
|
|
|
|
always @(state) begin
|
|
a_to_eab = OFF;
|
|
a_to_i = OFF;
|
|
a_to_old_x = OFF;
|
|
a_to_s = OFF;
|
|
a_to_x = OFF;
|
|
alu_mode = PLUS;
|
|
alu_res_to_a = OFF;
|
|
alu_set_c = OFF;
|
|
alu_set_s = OFF;
|
|
alu_set_z = OFF;
|
|
din_to_a = OFF;
|
|
div_to_b_shift_1 = OFF;
|
|
edb_to_din = OFF;
|
|
i_to_a = OFF;
|
|
k0_to_a = OFF;
|
|
k1_to_b = OFF;
|
|
old_x_to_b = OFF;
|
|
s_to_a_shift_1 = OFF;
|
|
s_to_b = OFF;
|
|
x_to_a = OFF;
|
|
x_to_b_shifted = OFF;
|
|
|
|
ready = OFF;
|
|
ram_rd_en = OFF;
|
|
ram_wr_en = OFF;
|
|
|
|
case (state)
|
|
`IDLE: begin
|
|
ready = ON;
|
|
end
|
|
`LD_N_1: begin
|
|
k0_to_a = ON;
|
|
a_to_eab = ON;
|
|
edb_to_din = ON;
|
|
ram_rd_en = ON;
|
|
end
|
|
`LD_N_2: begin
|
|
din_to_a = ON;
|
|
k0_to_a = ON;
|
|
alu_mode = MINUS;
|
|
alu_set_z = ON;
|
|
end
|
|
`I_GT_ZERO: begin
|
|
alu_res_to_a = ON;
|
|
a_to_i = ON;
|
|
end
|
|
`LD_S_1: begin
|
|
i_to_a = ON;
|
|
edb_to_din = ON;
|
|
a_to_eab = ON;
|
|
ram_rd_en = ON;
|
|
end
|
|
`LD_S_2: begin
|
|
din_to_a = ON;
|
|
a_to_s = ON;
|
|
k1_to_b = ON;
|
|
alu_mode = MINUS;
|
|
alu_set_s = ON;
|
|
alu_set_z = ON;
|
|
end
|
|
`S_GT_ONE:; // noop
|
|
`X_1: begin
|
|
s_to_a_shift_1 = ON;
|
|
s_to_b = ON;
|
|
|
|
a_to_old_x = ON;
|
|
a_to_x = ON;
|
|
end
|
|
`DIV_1: begin
|
|
x_to_a = ON;
|
|
s_to_b = ON;
|
|
end
|
|
`DIV_2:; // noop
|
|
`DIV_3:; // noop
|
|
`DIV_4: begin
|
|
x_to_a = ON;
|
|
div_to_b_shift_1 = ON;
|
|
end
|
|
`OLD_X_LTE_X_1: begin
|
|
alu_res_to_a = ON;
|
|
a_to_x = ON;
|
|
old_x_to_b = ON;
|
|
alu_set_c = ON;
|
|
end
|
|
`OLD_X_LTE_X_2: begin
|
|
x_to_a = ON;
|
|
a_to_old_x = ON;
|
|
end
|
|
`STORE_X: begin
|
|
x_to_b_shifted = ON;
|
|
ram_wr_en = ON;
|
|
end
|
|
`DEC_I: begin
|
|
i_to_a = ON;
|
|
k1_to_b = ON;
|
|
alu_mode = MINUS;
|
|
alu_set_z = ON;
|
|
end
|
|
endcase
|
|
end
|
|
endmodule
|