first verilog project
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#
#Busse
#
#- BUS_A (Ad)
#- BUS_B
#- BUS_C
#
#- EDB (Externer Datenbus)
#- EAB (Externer Adressbus)
#
#Register
#
#- I (Schleifenzähler)
#
#- ADR (Adressregister)
#- DIN (Data In)
#- DO (Data out)
#
#Rechenwerke
#
#ALU -> ALU_A, ALU_B
#DIV -> DIV_A, DIV_B
|--+-------------------|
| | NA |
| | X-X |
| | BC: |
| | -> Load=0: IDLE |
| | -> Load=1: LD_N_1 |
| | Idle |
|--+-------------------|
|-------------------+-----------|
| 0 -> BUS_B -> ADR | DR |
| EDB -> DIN | N/A - N/A |
| | LD_N_2 |
| | LD_N_1 |
|-------------------+-----------|
|-----------------------+--------------|
| DIN -> BUS_A -> ALU_A | NA |
| 0 -> BUS_B -> ALU_B | SUB - Z: SET |
| | N/A - N/A |
| | I_GT_ZERO |
| | LD_N_2 |
|-----------------------+--------------|
|-------------------+------------------|
| DIN -> BUS_A -> I | NA |
| | N/A - N/A |
| | BC: |
| | -> Z = 0: LD_S_1 |
| | -> Z = 1: IDLE |
| | I_GT_ZERO |
|-------------------+------------------|
|-------------------+-----------|
| I -> BUS_A -> ADR | DR |
| EDB -> DIN | N/A - N/A |
| | LD_S_2 |
| | LD_S_1 |
|-------------------+-----------|
|-----------------------+--------------|
| DIN -> BUS_A -> S | N/A |
| DIN -> BUS_A -> ALU_A | SUB - S: SET |
| 1 -> BUS_B -> ALU_B | - Z: SET |
| | S_GT_ONE |
| | LD_S_2 |
|-----------------------+--------------|
|--+------------------------|
| | N/A |
| | N/A |
| | BC: |
| | -> S=0 and Z=0: X_1 |
| | -> S=1 or Z=1: STORE_X |
| | S_GT_ONE |
|--+------------------------|
|-------------------------------+-------|
| S_{shift 1} -> BUS_A -> DIV_A | N/A |
| S_{shift 1} -> BUS_A -> X | N/A |
| S_{shift 1} -> BUS_A -> OLD_X | DIV_2 |
| S -> BUS_B -> DIV_B | X_1 |
|-------------------------------+-------|
|---------------------+-------|
| X -> BUS_A -> DIV_A | N/A |
| S -> BUS_B -> DIV_B | N/A |
| | DIV_2 |
| | DIV_1 |
|---------------------+-------|
|--+-------|
| | N/A |
| | N/A |
| | DIV_3 |
| | DIV_2 |
|--+-------|
|--+-------|
| | N/A |
| | N/A |
| | DIV_4 |
| | DIV_3 |
|--+-------|
|---------------------------------+---------------|
| X -> BUS_A -> ALU_A | N/A |
| DIV_{shift 1} -> BUS_B -> ALU_B | ADD - N/A |
| | OLD_X_LTE_X_1 |
| | DIV_4 |
|---------------------------------+---------------|
|-------------------------+---------------|
| ALU -> BUS_A -> X | N/A |
| ALU -> BUS_A -> ALU_A | SUB - C: SET |
| OLD_X -> BUS_B -> ALU_B | OLD_X_LTE_X_2 |
| | OLD_X_LTE_X_1 |
|-------------------------+---------------|
|---------------------+-----------------|
| X -> BUS_A -> OLD_X | N/A |
| | N/A |
| | BC: |
| | -> C=1: DIV_1 |
| | -> C=0: STORE_X |
| | OLD_X_LTE_X_2 |
|---------------------+-----------------|
|----------------------------+---------|
| X (shifted) -> BUS_A -> DO | DW |
| | N/A |
| | DEC_I |
| | STORE_X |
|----------------------------+---------|
|---------------------+--------------|
| I -> BUS_A -> ALU_A | N/A |
| 1 -> BUS_B -> ALU_B | SUB - Z: SET |
| | I_GT_ZERO |
| | DEC_I |
|---------------------+--------------|