40 lines
489 B
Verilog
40 lines
489 B
Verilog
module heron_ctrl(
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state,
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ready,
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ram_wr_en,
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ram_rd_en,
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alu_mode,
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alu_set_z,
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alu_set_c,
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alu_set_s,
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k0_to_b,
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k1_to_b,
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alu_to_b,
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a_to_adr,
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a_to_i,
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a_to_old_x,
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a_to_s,
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a_to_x,
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b_to_adr,
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din_to_a,
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div_to_b_shift_1,
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i_to_a,
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old_x_to_b,
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s_to_b,
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s_to_b_shift_1,
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x_to_a,
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x_to_b_shifted);
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input [3:0] state;
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output ready;
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output ram_wr_en;
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output ram_rd_en;
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output rom_rd_en;
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output alu_mode;
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always @(state) begin
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end
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endmodule
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