first verilog project
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module heron_ctrl(
state,
ready,
ram_wr_en,
ram_rd_en,
alu_mode,
alu_set_z,
alu_set_c,
alu_set_s,
k0_to_b,
k1_to_b,
alu_to_b,
a_to_adr,
a_to_i,
a_to_old_x,
a_to_s,
a_to_x,
b_to_adr,
din_to_a,
div_to_b_shift_1,
i_to_a,
old_x_to_b,
s_to_b,
s_to_b_shift_1,
x_to_a,
x_to_b_shifted);
input [3:0] state;
output ready;
output ram_wr_en;
output ram_rd_en;
output rom_rd_en;
output alu_mode;
always @(state) begin
end
endmodule