81 lines
2.0 KiB
Verilog
81 lines
2.0 KiB
Verilog
module heron_fsm(clk, load, reset, flag_z, flag_c, flag_s, state);
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// (C) 1953, Frank Gray
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parameter IDLE = 4'b0000;
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parameter LD_N_1 = 4'b0001;
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parameter LD_N_2 = 4'b0011;
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parameter I_GT_ZERO = 4'b0010;
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parameter LD_S_1 = 4'b0110;
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parameter LD_S_2 = 4'b0111;
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parameter S_GT_ONE = 4'b0101;
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parameter X_1 = 4'b0100;
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parameter DIV_1 = 4'b1100;
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parameter DIV_2 = 4'b1101;
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parameter DIV_3 = 4'b1111;
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parameter DIV_4 = 4'b1110;
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parameter OLD_X_LTE_X_1 = 4'b1010;
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parameter OLD_X_LTE_X_2 = 4'b1011;
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parameter STORE_X = 4'b1001;
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parameter DEC_I = 4'b1000;
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input clk;
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input load;
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input reset;
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input flag_z;
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input flag_c;
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input flag_s;
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output [3:0] state;
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reg [3:0] state;
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reg [3:0] next_state;
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always @(posedge clk or posedge reset)
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if(reset) begin
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state <= IDLE;
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end else begin
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state <= next_state;
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end
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always @(state or flag_z or load)
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case(state)
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IDLE:
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if(load) begin
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next_state = LD_N_1;
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end else begin
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next_state = IDLE;
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end
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LD_N_1: next_state = LD_N_2;
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LD_N_2: next_state = I_GT_ZERO;
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I_GT_ZERO:
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if (flag_z) begin
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next_state = LD_S_1;
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end else begin
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next_state = IDLE;
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end
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LD_S_1: next_state = LD_S_2;
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LD_S_2: next_state = S_GT_ONE;
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S_GT_ONE:
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if (flag_s || flag_z) begin
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next_state = STORE_X;
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end else begin
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next_state = X_1;
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end
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X_1: next_state = DIV_2;
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DIV_1: next_state = DIV_2;
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DIV_2: next_state = DIV_3;
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DIV_3: next_state = DIV_4;
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DIV_4: next_state = OLD_X_LTE_X_1;
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OLD_X_LTE_X_1: next_state = OLD_X_LTE_X_2;
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OLD_X_LTE_X_2:
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if (flag_c) begin
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next_state = DIV_1;
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end else begin
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next_state = STORE_X;
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end
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STORE_X: next_state = DEC_I;
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DEC_I: next_state = I_GT_ZERO;
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endcase
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end
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endmodule
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