heron_sqrt/verilog/heron_comma_fix.v

12 lines
247 B
Verilog

module heron_comma_fix (A,Y);
parameter comma = 8;
parameter comma_fix = comma / 2;
input [31:0] A;
output [31:0] Y;
wire [31:0] Y;
assign Y[(31 - comma_fix):0] = A[(31 - comma_fix):0];
assign Y[31:(31 - comma_fix)] = 0;
endmodule