heron_sqrt/cadence/heron_ctrl_tb/functional/verilog.v

module heron_fsm_tb;
  task assert;
    input condition;
    input [(20*8 - 1):0] message;
    begin
      if (condition !== 1'b1)
      begin
        $display("Assertion Failed: %s", message);
        $finish(2);
      end
    end
  endtask

  reg[3:0] state;

  initial begin
    $dumpfile("ctrl.vcd");
    $dumpvars;
  end

  initial begin
    $display("Control logic tests passed!");
    $finish;
  end
end