heron_sqrt/cadence/heron_ctrl/functional/verilog.v

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`include "heron_states.v"
module heron_ctrl(
ctrl_bus,
state,
ready,
ram_rd_en,
ram_wr_en);
// readability
parameter ON = 1'b1;
parameter OFF = 1'b0;
parameter MINUS = 1'b1;
input [3:0] state;
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output ready;
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reg ready = OFF;
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output ram_rd_en, ram_wr_en;
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reg ram_rd_en = OFF;
reg ram_wr_en = OFF;
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output [22:0] ctrl_bus;
`define CTRL_WIRE(name,port) \
reg name; \
assign ctrl_bus[port] = name;
`include "heron_ctrl_wires.v"
`undef CTRL_WIRE
always @(state) begin
ready = OFF;
ram_rd_en = OFF;
ram_wr_en = OFF;
`define CTRL_WIRE(name,port) name = OFF;
`include "heron_ctrl_wires.v"
`undef CTRL_WIRE
case (state)
`IDLE: begin
ready = ON;
end
`LD_N_1: begin
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ram_rd_en = ON;
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k0_to_a = ON;
a_to_eab = ON;
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edb_to_din = ON;
end
`LD_N_2: begin
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alu_set_z = ON;
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din_to_a = ON;
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k0_to_b = ON;
end
`I_GT_ZERO: begin
alu_res_to_a = ON;
a_to_i = ON;
end
`LD_S_1: begin
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ram_rd_en = ON;
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i_to_a = ON;
a_to_eab = ON;
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edb_to_din = ON;
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end
`LD_S_2: begin
alu_mode = MINUS;
alu_set_s = ON;
alu_set_z = ON;
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din_to_a = ON;
a_to_s = ON;
k1_to_b = ON;
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end
`S_GT_ONE:; // noop
`X_1: begin
s_to_a_shift_1 = ON;
a_to_old_x = ON;
a_to_x = ON;
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s_to_b = ON;
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end
`DIV_1: begin
x_to_a = ON;
s_to_b = ON;
end
`DIV_2:; // noop
`DIV_3:; // noop
`DIV_4: begin
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x_to_a_shift_1 = ON;
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div_to_b_shift_1 = ON;
end
`OLD_X_LTE_X_1: begin
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alu_mode = MINUS;
alu_set_c = ON;
alu_set_z = ON;
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alu_res_to_a = ON;
a_to_x = ON;
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old_x_to_b = ON;
end
`OLD_X_LTE_X_2: begin
x_to_a = ON;
a_to_old_x = ON;
end
`STORE_X: begin
ram_wr_en = ON;
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i_to_a = ON;
a_to_eab = ON;
x_to_b_shifted = ON;
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end
`DEC_I: begin
alu_mode = MINUS;
alu_set_z = ON;
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i_to_a = ON;
k1_to_b = ON;
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end
endcase
end
endmodule