heron_sqrt/verilog/heron_top_tb.v

module heron_top_tb ( );
  task assert;
    input condition;
    input [(20*8 - 1):0] message;
    begin
      if (condition !== 1'b1)
      begin
        $display("Assertion Failed: %s", message);
        $finish(2);
      end
    end
  endtask

  parameter CYCLE = 50;

  wire  [31:0] edb;
  wire  [31:0] eab;
  wire  ready;
  wire  ram_wr_en;
  wire  ram_rd_en;

  reg clk, reset;
  reg load;

  reg [31:0] ram [0:1023];

  heron_top heron(
    .eab(eab),
    .edb(edb),
    .clk(clk),
    .reset(reset),
    .ram_wr_en(ram_wr_en),
    .ram_rd_en(ram_rd_en),
    .ready(ready),
    .load(load)
  );

endmodule