heron_sqrt/verilog/heron_scaler64_to_32.v

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2014-01-10 12:22:11 +00:00
module heron_scaler64_to_32 (A,Y);
input [63:0] A;
output [31:0] Y;
wire [31:0] Y;
assign Y[30:0] = A[63:33];
assign Y[31] = 0;
endmodule