heron_sqrt/verilog/heron_fsm.v

`include "heron_states.v"

module heron_fsm(clk, load, reset, flag_z, flag_c, flag_s, state);
  input clk;
  input load;
  input reset;

  input flag_z;
  input flag_c;
  input flag_s;

  output [3:0] state;

  reg [3:0] state;
  reg [3:0] next_state;

  always @(posedge clk or posedge reset)
    if(reset) begin
      state <= `IDLE;
    end else begin
      state <= next_state;
    end

  always @(state or flag_z or load)
    case(state)
      `IDLE: begin
        if(load) begin
          next_state = `LD_N_1;
        end else begin
          next_state = `IDLE;
        end
      end
      `LD_N_1: next_state = `LD_N_2;
      `LD_N_2: next_state = `I_GT_ZERO;
      `I_GT_ZERO: begin
        if (flag_z) begin
          next_state = `LD_S_1;
        end else begin
          next_state = `IDLE;
        end
      end
      `LD_S_1: next_state = `LD_S_2;
      `LD_S_2: next_state = `S_GT_ONE;
      `S_GT_ONE: begin
        if (flag_s || flag_z) begin
          next_state = `STORE_X;
        end else begin
          next_state = `X_1;
        end
      end
      `X_1: next_state = `DIV_2;
      `DIV_1: next_state = `DIV_2;
      `DIV_2: next_state = `DIV_3;
      `DIV_3: next_state = `DIV_4;
      `DIV_4: next_state = `OLD_X_LTE_X_1;
      `OLD_X_LTE_X_1: next_state = `OLD_X_LTE_X_2;
      `OLD_X_LTE_X_2: begin
        if (flag_c) begin
          next_state = `DIV_1;
        end else begin
          next_state = `STORE_X;
        end
      end
      `STORE_X: next_state = `DEC_I;
      `DEC_I: next_state = `I_GT_ZERO;
    endcase
endmodule