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fix loop breaker condition

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Jörg Thalheim 2015-01-14 10:39:45 +01:00
parent 162bb47d24
commit 922124b0bf
2 changed files with 20 additions and 15 deletions
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29
bericht/rt_folgen.txt
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@ -113,21 +113,22 @@
| | DIV_4 | | | DIV_4 |
|---------------------------------+---------------| |---------------------------------+---------------|
|---------------------------+---------------|
| ALU_RES -> BUS_A -> X | N/A |
| ALU_RES -> BUS_A -> ALU_A | SUB - C: SET |
| OLD_X -> BUS_B -> ALU_B | OLD_X_LTE_X_2 |
| | OLD_X_LTE_X_1 |
|---------------------------+---------------|
|---------------------+-----------------| |---------------------------+----------------------|
| X -> BUS_A -> OLD_X | N/A | | ALU_RES -> BUS_A -> X | N/A |
| | N/A | | ALU_RES -> BUS_A -> ALU_A | SUB - C: SET, Z: SET |
| | BC: | | OLD_X -> BUS_B -> ALU_B | OLD_X_LTE_X_2 |
| | -> C=1: DIV_1 | | | OLD_X_LTE_X_1 | :
| | -> C=0: STORE_X | |---------------------------+----------------------|
| | OLD_X_LTE_X_2 |
|---------------------+-----------------| |---------------------+------------------------|
| X -> BUS_A -> OLD_X | N/A |
| | N/A |
| | BC: |
| | -> C=1 or Z=1: STORE_X |
| | -> C=0: DIV_1 |
| | OLD_X_LTE_X_2 |
|---------------------+------------------------|
|----------------------------+---------| |----------------------------+---------|
| X (shifted) -> BUS_A -> DO | DW | | X (shifted) -> BUS_A -> DO | DW |

6
cadence/heron_ctrl/functional/verilog.v
View File

@ -89,10 +89,14 @@ module heron_ctrl(
div_to_b_shift_1 = ON; div_to_b_shift_1 = ON;
end end
`OLD_X_LTE_X_1: begin `OLD_X_LTE_X_1: begin
alu_mode = MINUS;
alu_set_c = ON;
alu_set_z = ON;
alu_res_to_a = ON; alu_res_to_a = ON;
a_to_x = ON; a_to_x = ON;
old_x_to_b = ON; old_x_to_b = ON;
alu_set_c = ON;
end end
`OLD_X_LTE_X_2: begin `OLD_X_LTE_X_2: begin
x_to_a = ON; x_to_a = ON;