26 lines
411 B
Verilog
26 lines
411 B
Verilog
module heron_fsm_tb;
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task assert;
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input condition;
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input [(20*8 - 1):0] message;
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begin
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if (condition !== 1'b1)
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begin
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$display("Assertion Failed: %s", message);
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$finish(2);
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end
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end
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endtask
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reg[3:0] state;
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initial begin
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$dumpfile("ctrl.vcd");
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$dumpvars;
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end
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initial begin
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$display("Control logic tests passed!");
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$finish;
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end
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end
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