first verilog project
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38 lines
698 B

module SQRT(A, Y, clk, reset);
parameter width = 31;
`define width 31
input [width:0] A;
reg [width:0] x;
reg [width:0] old_x;
output [width:0] Y;
always @(A)
begin
case(state)
WAIT: Y = 0;
CALC1:
x = CALC1
state = OUTPUT
CALC2:
if (old_x <= x) begin
state = OUTPUT
end
OUTPUT: Y = Y_t;
default: Y = 0;
endcase
end
initial begin : parameter_check
if (width < 1) begin
$display("ERROR: %m :\n Invalid value (%d) for parameter width (lower bound: 1)", width);
$finish;
end
if (width > 32) begin
$display("ERROR: %m :\n Invalid value (%d) for parameter width (upper bound: 32)", width);
$finish;
end
end
endmodule