first verilog project

Jörg Thalheim 33b786ec46 Makefile: automating testbench		2014-01-18 11:59:36 +01:00
bericht	.	2014-01-13 09:08:21 +01:00
c	.	2014-01-13 09:08:21 +01:00
cadence	add cadence verilog code	2014-01-18 11:59:04 +01:00
verilog	.	2014-01-13 09:08:21 +01:00
.gitignore	gitignore cadence	2014-01-18 11:59:19 +01:00
Makefile	Makefile: automating testbench	2014-01-18 11:59:36 +01:00