40 lines
614 B
Verilog
40 lines
614 B
Verilog
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module heron_top_tb ( );
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task assert;
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input condition;
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input [(20*8 - 1):0] message;
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begin
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if (condition !== 1'b1)
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begin
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$display("Assertion Failed: %s", message);
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$finish(2);
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end
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end
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endtask
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parameter CYCLE = 50;
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wire [31:0] edb;
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wire [31:0] eab;
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wire ready;
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wire ram_wr_en;
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wire ram_rd_en;
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reg clk, reset;
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reg load;
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reg [31:0] ram [0:1023];
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heron_top heron(
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.eab(eab),
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.edb(edb),
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.clk(clk),
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.reset(reset),
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.ram_wr_en(ram_wr_en),
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.ram_rd_en(ram_rd_en),
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.ready(ready),
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.load(load)
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);
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endmodule
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