39 lines
698 B
Verilog
39 lines
698 B
Verilog
module SQRT(A, Y, clk, reset);
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parameter width = 31;
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`define width 31
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input [width:0] A;
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reg [width:0] x;
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reg [width:0] old_x;
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output [width:0] Y;
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always @(A)
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begin
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case(state)
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WAIT: Y = 0;
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CALC1:
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x = CALC1
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state = OUTPUT
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CALC2:
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if (old_x <= x) begin
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state = OUTPUT
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end
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OUTPUT: Y = Y_t;
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default: Y = 0;
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endcase
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end
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initial begin : parameter_check
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if (width < 1) begin
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$display("ERROR: %m :\n Invalid value (%d) for parameter width (lower bound: 1)", width);
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$finish;
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end
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if (width > 32) begin
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$display("ERROR: %m :\n Invalid value (%d) for parameter width (upper bound: 32)", width);
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$finish;
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end
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end
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endmodule
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