67 lines
1.1 KiB
Verilog
67 lines
1.1 KiB
Verilog
`include "heron_states.v"
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module heron_fsm_tb;
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task assert;
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input condition;
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input [(20*8 - 1):0] message;
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begin
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if (condition !== 1'b1)
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begin
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$display("Assertion Failed: %s", message);
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$finish(2);
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end
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end
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endtask
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parameter CYCLE = 50;
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reg clk, reset;
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reg load;
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reg flag_z, flag_c, flag_s;
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wire[3:0] state;
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heron_fsm fsm(
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.clk(clk),
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.reset(reset),
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.load(load),
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.state(state),
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.flag_z(flag_z),
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.flag_c(flag_c),
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.flag_s(flag_s)
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);
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initial clk = 1'b0;
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always #(CYCLE/2) clk = ~clk;
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initial begin
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$dumpfile("fsm.vcd");
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$dumpvars;
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end
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initial begin
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reset = 1'b1;
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#(3*CYCLE)
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reset = 1'b0;
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end
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initial begin
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load = 0;
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#(5*CYCLE)
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load = 1;
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#(CYCLE)
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load = 0;
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assert(state == `LD_N_1, "IDLE -> LD_N_1");
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#(CYCLE)
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assert(state == `LD_N_2, "LD_N_1 -> LD_N_2");
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#(CYCLE)
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assert(state == `I_GT_ZERO, "LD_N_2 -> I_GT_ZERO");
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#(CYCLE)
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assert(state == `I_GT_ZERO, "LD_N_2 -> I_GT_ZERO");
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$display("FSM tests passed!");
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$finish;
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end
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endmodule
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