heron_sqrt/cadence/heron_shift_1/functional/verilog.v

11 lines
140 B
Verilog

module heron_shift_1 (A, Y);
input [31:0] A;
output [31:0] Y;
wire [31:0] Y;
assign Y[30:0] = A[31:1];
assign Y[31] = 0;
endmodule