198 lines
3.6 KiB
Verilog
198 lines
3.6 KiB
Verilog
`include "heron_states.v"
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module heron_ctrl(
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state, // ?
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ready, // ?
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ram_wr_en, // ?
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ram_rd_en, // ?
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alu_mode, //
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alu_set_z, //
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alu_set_c, //
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alu_set_s, //
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k0_to_b, //
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k1_to_b, //
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alu_res_to_a, //
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a_to_adr,
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a_to_i, //
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a_to_old_x, //
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a_to_s, //
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a_to_x, //
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b_to_adr, // ?
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din_to_a, // ?
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edb_to_din, // ?
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a_to_do, // ?
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div_to_b_shift_1, // ?
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i_to_a, //
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old_x_to_b, //
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s_to_b, //
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s_to_a_shift_1, //
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x_to_a, //
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x_to_b_shifted); // ?
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// readability
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parameter ON = 1'b1;
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parameter OFF = 1'b0;
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parameter MINUS = 1'b1;
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parameter PLUS = 1'b0;
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input [3:0] state;
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output ready;
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output ram_wr_en;
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output ram_rd_en;
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output alu_mode;
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output alu_set_z;
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output alu_set_c;
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output alu_set_s;
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output k0_to_b;
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output k1_to_b;
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output alu_res_to_a;
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output a_to_adr;
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output a_to_i;
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output a_to_old_x;
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output a_to_s;
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output a_to_x;
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output b_to_adr;
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output din_to_a;
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output edb_to_din;
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output a_to_do;
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output div_to_b_shift_1;
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output i_to_a;
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output old_x_to_b;
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output s_to_b;
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output s_to_a_shift_1;
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output x_to_a;
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output x_to_b_shifted;
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reg ready;
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reg ram_wr_en;
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reg ram_rd_en;
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reg rom_rd_en;
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reg alu_mode;
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reg alu_set_z;
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reg alu_set_c;
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reg alu_set_s;
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reg k0_to_b;
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reg k1_to_b;
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reg alu_res_to_a;
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reg a_to_adr;
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reg a_to_i;
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reg a_to_old_x;
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reg a_to_s;
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reg a_to_x;
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reg b_to_adr;
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reg din_to_a;
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reg edb_to_din;
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reg a_to_do;
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reg div_to_b_shift_1;
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reg i_to_a;
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reg old_x_to_b;
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reg s_to_b;
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reg s_to_a_shift_1;
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reg x_to_a;
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reg x_to_b_shifted;
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always @(state) begin
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ready = OFF;
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ram_wr_en = OFF;
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ram_rd_en = OFF;
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alu_mode = PLUS;
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alu_set_z = OFF;
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alu_set_c = OFF;
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alu_set_s = OFF;
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k0_to_b = OFF;
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k1_to_b = OFF;
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alu_res_to_a = OFF;
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a_to_adr = OFF;
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a_to_i = OFF;
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a_to_old_x = OFF;
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a_to_s = OFF;
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a_to_x = OFF;
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b_to_adr = OFF;
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din_to_a = OFF;
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edb_to_din = OFF;
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div_to_b_shift_1 = OFF;
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i_to_a = OFF;
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old_x_to_b = OFF;
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s_to_b = OFF;
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s_to_a_shift_1 = OFF;
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x_to_a = OFF;
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x_to_b_shifted = OFF;
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case (state)
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`IDLE: begin
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ready = ON;
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end
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`LD_N_1: begin
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k0_to_b = ON;
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b_to_adr = ON;
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edb_to_din = ON;
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ram_rd_en = ON;
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end
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`LD_N_2: begin
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din_to_a = ON;
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k0_to_b = ON;
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alu_mode = MINUS;
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alu_set_z = ON;
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end
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`I_GT_ZERO: begin
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alu_res_to_a = ON;
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a_to_i = ON;
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end
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`LD_S_1: begin
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i_to_a = ON;
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edb_to_din = ON;
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a_to_adr = ON;
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ram_rd_en = ON;
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end
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`LD_S_2: begin
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din_to_a = ON;
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a_to_s = ON;
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k1_to_b = ON;
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alu_mode = MINUS;
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alu_set_s = ON;
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alu_set_z = ON;
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end
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`S_GT_ONE:; // noop
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`X_1: begin
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s_to_a_shift_1 = ON;
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s_to_b = ON;
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a_to_old_x = ON;
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a_to_x = ON;
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end
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`DIV_1: begin
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x_to_a = ON;
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s_to_b = ON;
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end
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`DIV_2:; // noop
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`DIV_3:; // noop
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`DIV_4: begin
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x_to_a = ON;
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div_to_b_shift_1 = ON;
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end
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`OLD_X_LTE_X_1: begin
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alu_res_to_a = ON;
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a_to_x = ON;
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old_x_to_b = ON;
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alu_set_c = ON;
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end
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`OLD_X_LTE_X_2: begin
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x_to_a = ON;
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a_to_old_x = ON;
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end
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`STORE_X: begin
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x_to_b_shifted = ON;
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a_to_do = ON;
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ram_wr_en = ON;
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end
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`DEC_I: begin
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i_to_a = ON;
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k1_to_b = ON;
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alu_mode = MINUS;
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alu_set_z = ON;
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end
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endcase
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end
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endmodule
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