heron_sqrt/cadence/heron_ctrl/functional/verilog.v

114 lines
2.1 KiB
Verilog

`include "heron_states.v"
module heron_ctrl(
ctrl_bus,
// rest
state,
ready,
ram_rd_en,
ram_wr_en);
// readability
parameter ON = 1'b1;
parameter OFF = 1'b0;
parameter MINUS = 1'b1;
input [3:0] state;
output ready;
output ram_rd_en, ram_wr_en;
output [22:0] ctrl_bus;
`define CTRL_WIRE(name,port) \
reg name; \
assign ctrl_bus[port] = name;
`include "heron_ctrl_wires.v"
`undef CTRL_WIRE
reg ready = OFF;
reg ram_rd_en = OFF;
reg ram_wr_en = OFF;
always @(state) begin
ready = OFF;
ram_rd_en = OFF;
ram_wr_en = OFF;
`define CTRL_WIRE(name,port) name = OFF;
`include "heron_ctrl_wires.v"
`undef CTRL_WIRE
case (state)
`IDLE: begin
ready = ON;
end
`LD_N_1: begin
k0_to_a = ON;
a_to_eab = ON;
edb_to_din = ON;
ram_rd_en = ON;
end
`LD_N_2: begin
din_to_a = ON;
k0_to_b = ON;
alu_set_z = ON;
end
`I_GT_ZERO: begin
alu_res_to_a = ON;
a_to_i = ON;
end
`LD_S_1: begin
i_to_a = ON;
edb_to_din = ON;
a_to_eab = ON;
ram_rd_en = ON;
end
`LD_S_2: begin
din_to_a = ON;
a_to_s = ON;
k1_to_b = ON;
alu_mode = MINUS;
alu_set_s = ON;
alu_set_z = ON;
end
`S_GT_ONE:; // noop
`X_1: begin
s_to_a_shift_1 = ON;
s_to_b = ON;
a_to_old_x = ON;
a_to_x = ON;
end
`DIV_1: begin
x_to_a = ON;
s_to_b = ON;
end
`DIV_2:; // noop
`DIV_3:; // noop
`DIV_4: begin
x_to_a = ON;
div_to_b_shift_1 = ON;
end
`OLD_X_LTE_X_1: begin
alu_res_to_a = ON;
a_to_x = ON;
old_x_to_b = ON;
alu_set_c = ON;
end
`OLD_X_LTE_X_2: begin
x_to_a = ON;
a_to_old_x = ON;
end
`STORE_X: begin
x_to_b_shifted = ON;
ram_wr_en = ON;
end
`DEC_I: begin
i_to_a = ON;
k1_to_b = ON;
alu_mode = MINUS;
alu_set_z = ON;
end
endcase
end
endmodule