heron_sqrt/cadence/heron_scaler64_to_32/functional/verilog.v

8 lines
148 B
Verilog

module heron_scaler64_to_32 (A,Y);
input [63:0] A;
output [31:0] Y;
wire [31:0] Y;
assign Y[30:0] = A[63:33];
assign Y[31] = 0;
endmodule