126 lines
2.3 KiB
Verilog
126 lines
2.3 KiB
Verilog
`include "heron_states.v"
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module heron_top_tb();
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`define ASSERT(c, msg) if (!c) begin $display("%c[31mAssertion Failed: %s%c[0m", 27, msg, 27); $finish(2); end
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`define ASSERT_STATE(state) `ASSERT((fsm_state == state), "not expected state")
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parameter CYCLE = 50;
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wire [31:0] edb;
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wire [31:0] eab;
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wire ready;
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wire ram_wr_en, ram_rd_en;
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wire [3:0] fsm_state;
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assign fsm_state = heron.fsm.state;
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reg reset;
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reg load = 0;
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reg [15:0] i;
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reg clk = 1'b0;
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always #(CYCLE/2) clk = ~clk;
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reg [31:0] ram [0:1023];
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wire ram0;
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wire ram1;
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wire ram2;
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assign ram0 = ram[0];
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assign ram1 = ram[1];
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assign ram2 = ram[2];
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assign edb = ram_rd_en ? ram[eab[9:0]] : 32'bz;
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always @ (posedge clk) begin
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if (ram_wr_en) begin
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ram[eab[9:0]] <= edb;
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end
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end
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heron_top heron(
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.clk(clk),
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.load(load),
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.reset(reset),
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.edb(edb),
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.eab(eab),
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.ram_rd_en(ram_rd_en),
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.ram_wr_en(ram_wr_en),
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.ready(ready)
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);
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initial begin
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$dumpfile("heron_top_tb.vcd");
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$dumpvars;
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ram[0] = 3;
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ram[3] = 4;
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ram[2] = 0;
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ram[1] = 1;
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end
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initial begin
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`ASSERT_STATE(`IDLE)
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#(5*CYCLE)
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load = 1;
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#(CYCLE)
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load = 0;
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// load mem[0] -> number of operands
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`ASSERT_STATE(`LD_N_1)
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#(CYCLE)
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// load...
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`ASSERT_STATE(`LD_N_2)
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#(CYCLE)
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// if (mem[0] > 0) then
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`ASSERT_STATE(`I_GT_ZERO)
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#(CYCLE)
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// load mem[1]...
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`ASSERT_STATE(`LD_S_1)
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#(CYCLE)
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// ...load
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`ASSERT_STATE(`LD_S_2)
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#(CYCLE)
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// if (mem[1] > 1) then
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`ASSERT_STATE(`S_GT_ONE)
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#(CYCLE)
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// x_0 = s / 2
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`ASSERT_STATE(`X_1)
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#(CYCLE)
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// s / x_n...
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`ASSERT_STATE(`DIV_2)
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#(CYCLE)
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// ..divide
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`ASSERT_STATE(`DIV_3)
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#(CYCLE)
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// x_1 = x_n + (s / x_n) / 2
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`ASSERT_STATE(`DIV_4)
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#(CYCLE)
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// if (old_x <= x_1) ...
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`ASSERT_STATE(`OLD_X_LTE_X_1)
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#(CYCLE)
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// ... then
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`ASSERT_STATE(`OLD_X_LTE_X_2)
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#(CYCLE)
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// store mem[1] = 2
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`ASSERT_STATE(`STORE_X)
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#(CYCLE)
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// i--
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`ASSERT(ram[3] == 2, "sqrt(4) == 2")
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`ASSERT(ram[3] == 1, "sqrt(4) == 2")
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`ASSERT_STATE(`DEC_I)
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#(CYCLE)
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// if (i > 0) then ...
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`ASSERT_STATE(`I_GT_ZERO)
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for (i = 0; i < 1000; i = i + 1) begin
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if (ready != 0) begin
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$display("%c[32mSUCCESS: heron_top_tb tests bench finished;%c[0m", 27, 27);
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$finish;
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end
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#(CYCLE) ;
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end
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$display("%c[31mFAILED: heron_top_tb tests timeout!%c[0m", 27, 27);
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$finish(1);
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end
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endmodule
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