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4
Makefile
View File

@ -31,9 +31,9 @@ ctrl_tb: verilog/heron_ctrl.vcd
VERILOG_FILES=${shell find . -name verilog.v -type f}
sync:
cd cadence; rsync --relative --verbose -e ssh $(VERILOG_FILES:./cadence/%=%) eeets2:/home2/vlsi13/joth13/ICPRO/ice/heron/units/heron/cdslib/heron/
cd cadence; rsync --relative --verbose --rsync-path=~/rsync-3.1.0/rsync -e ssh $(VERILOG_FILES:./cadence/%=%) eeets2:/home2/vlsi13/joth13/ICPRO/ice/heron/units/heron/cdslib/heron/
testbench:
ssh eeets2 $(PROJECT_ROOT)/df2/run-testbench.sh
rsync -av --inplace -avHz -e ssh eeets2:$(TB_ROOT)/heron_top_tb.vcd .
rsync -av --inplace --rsync-path=~/rsync-3.1.0/rsync -avHz -e ssh eeets2:$(TB_ROOT)/heron_top_tb.vcd .
gtkwave heron_top_tb.gtkw

31
bericht/rt_folgen.txt
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@ -107,28 +107,27 @@
|--+-------|
|---------------------------------+---------------|
| X_{shift 1} -> BUS_A -> ALU_A | N/A |
| X -> BUS_A -> ALU_A | N/A |
| DIV_{shift 1} -> BUS_B -> ALU_B | ADD - N/A |
| | OLD_X_LTE_X_1 |
| | DIV_4 |
|---------------------------------+---------------|
|---------------------------+---------------|
| ALU_RES -> BUS_A -> X | N/A |
| ALU_RES -> BUS_A -> ALU_A | SUB - C: SET |
| OLD_X -> BUS_B -> ALU_B | OLD_X_LTE_X_2 |
| | OLD_X_LTE_X_1 |
|---------------------------+---------------|
|---------------------------+----------------------|
| ALU_RES -> BUS_A -> X | N/A |
| ALU_RES -> BUS_A -> ALU_A | SUB - C: SET, Z: SET |
| OLD_X -> BUS_B -> ALU_B | OLD_X_LTE_X_2 |
| | OLD_X_LTE_X_1 | :
|---------------------------+----------------------|
|---------------------+------------------------|
| X -> BUS_A -> OLD_X | N/A |
| | N/A |
| | BC: |
| | -> C=1 or Z=1: STORE_X |
| | -> C=0: DIV_1 |
| | OLD_X_LTE_X_2 |
|---------------------+------------------------|
|---------------------+-----------------|
| X -> BUS_A -> OLD_X | N/A |
| | N/A |
| | BC: |
| | -> C=1: DIV_1 |
| | -> C=0: STORE_X |
| | OLD_X_LTE_X_2 |
|---------------------+-----------------|
|----------------------------+---------|
| X (shifted) -> BUS_A -> DO | DW |

5
cadence/heron_comma_fix/functional/verilog.v
View File

@ -2,10 +2,11 @@ module heron_comma_fix (A,Y);
parameter comma = 8;
parameter comma_fix = comma / 2;
input [31:0] A;
output [31:0] Y;
wire [31:0] Y;
assign Y[31: comma_fix] = A[31 - comma_fix: 0];
assign Y[(comma_fix - 1):0] = 1'b0;
assign Y[(31 - comma_fix):0] = A[(31 - comma_fix):0];
assign Y[31:(31 - comma_fix)] = 0;
endmodule

56
cadence/heron_ctrl/functional/verilog.v
View File

@ -2,6 +2,7 @@
module heron_ctrl(
ctrl_bus,
// rest
state,
ready,
ram_rd_en,
@ -13,13 +14,8 @@ module heron_ctrl(
parameter MINUS = 1'b1;
input [3:0] state;
output ready;
reg ready = OFF;
output ram_rd_en, ram_wr_en;
reg ram_rd_en = OFF;
reg ram_wr_en = OFF;
output [22:0] ctrl_bus;
`define CTRL_WIRE(name,port) \
@ -28,6 +24,9 @@ module heron_ctrl(
`include "heron_ctrl_wires.v"
`undef CTRL_WIRE
reg ready = OFF;
reg ram_rd_en = OFF;
reg ram_wr_en = OFF;
always @(state) begin
ready = OFF;
@ -43,49 +42,41 @@ module heron_ctrl(
ready = ON;
end
`LD_N_1: begin
ram_rd_en = ON;
k0_to_a = ON;
a_to_eab = ON;
edb_to_din = ON;
ram_rd_en = ON;
end
`LD_N_2: begin
alu_set_z = ON;
din_to_a = ON;
k0_to_b = ON;
alu_set_z = ON;
end
`I_GT_ZERO: begin
alu_res_to_a = ON;
a_to_i = ON;
end
`LD_S_1: begin
ram_rd_en = ON;
i_to_a = ON;
a_to_eab = ON;
edb_to_din = ON;
a_to_eab = ON;
ram_rd_en = ON;
end
`LD_S_2: begin
din_to_a = ON;
a_to_s = ON;
k1_to_b = ON;
alu_mode = MINUS;
alu_set_s = ON;
alu_set_z = ON;
din_to_a = ON;
a_to_s = ON;
k1_to_b = ON;
end
`S_GT_ONE:; // noop
`X_1: begin
s_to_a_shift_1 = ON;
s_to_b = ON;
a_to_old_x = ON;
a_to_x = ON;
s_to_b = ON;
end
`DIV_1: begin
x_to_a = ON;
@ -94,39 +85,28 @@ module heron_ctrl(
`DIV_2:; // noop
`DIV_3:; // noop
`DIV_4: begin
x_to_a_shift_1 = ON;
x_to_a = ON;
div_to_b_shift_1 = ON;
end
`OLD_X_LTE_X_1: begin
alu_mode = MINUS;
alu_set_c = ON;
alu_set_z = ON;
alu_res_to_a = ON;
a_to_x = ON;
old_x_to_b = ON;
alu_set_c = ON;
end
`OLD_X_LTE_X_2: begin
x_to_a = ON;
a_to_old_x = ON;
end
`STORE_X: begin
ram_wr_en = ON;
i_to_a = ON;
a_to_eab = ON;
x_to_b_shifted = ON;
ram_wr_en = ON;
end
`DEC_I: begin
i_to_a = ON;
k1_to_b = ON;
alu_mode = MINUS;
alu_set_z = ON;
i_to_a = ON;
k1_to_b = ON;
end
endcase
end

5
cadence/heron_ctrl_wires/functional/verilog.v
View File

@ -21,14 +21,13 @@ module heron_ctrl_wires (
s_to_a_shift_1,
s_to_b,
x_to_a,
x_to_a_shift_1,
x_to_b_shifted
);
input [22:0] ctrl_bus;
`define CTRL_WIRE(name,port) \
output name; \
assign name = ctrl_bus[port];
`include "heron_ctrl_wires.v"
assign name = ctrl_bus[port];
`include "heron_ctrl_wires.v"
`undef CTRL_WIRE
endmodule

40
cadence/heron_top_tb/functional/verilog.v
View File

@ -5,7 +5,6 @@ module heron_top_tb();
`define ASSERT_STATE(state) `ASSERT((fsm_state == state), "not expected state")
parameter CYCLE = 50;
parameter COMMA = 8;
wire [31:0] edb;
wire [31:0] eab;
@ -23,34 +22,15 @@ always #(CYCLE/2) clk = ~clk;
reg [31:0] ram [0:1023];
wire [31:0] ram0;
wire [31:0] ram1;
wire [31:0] ram2;
wire [31:0] ram3;
wire [31:0] ram4;
wire ram0;
wire ram1;
wire ram2;
assign ram0 = ram[0];
assign ram1 = ram[1];
assign ram2 = ram[2];
assign ram3 = ram[3];
assign ram4 = ram[4];
assign edb = ram_rd_en ? ram[eab[9:0]] : 32'bz;
task displayRam;
reg [15:0] j;
reg [32:0] after_comma;
begin
for (j = 1; j <= ram[0]; j = j + 1) begin
// display fixed point as decimal
after_comma = ((ram[j][COMMA] * 10000) >> 1) +
((ram[j][COMMA - 1] * 10000) >> 2) +
((ram[j][COMMA - 2] * 10000) >> 3) +
((ram[j][COMMA - 3] * 10000) >> 4);
$display("ram[%d] = %d.%d (0x%h)", j, ram[j] >> COMMA, after_comma, ram[j]);
end
end
endtask
always @ (posedge clk) begin
if (ram_wr_en) begin
ram[eab[9:0]] <= edb;
@ -72,21 +52,17 @@ initial begin
$dumpfile("heron_top_tb.vcd");
$dumpvars;
ram[0] = 4;
ram[4] = 16 << COMMA;
ram[3] = 4 << COMMA;
ram[0] = 3;
ram[3] = 4;
ram[2] = 0 << COMMA;
ram[1] = 1 << COMMA;
ram[2] = 0;
ram[1] = 1;
end
initial begin
`ASSERT_STATE(`IDLE)
#(5*CYCLE)
load = 1;
reset = 1'b1;
#(CYCLE)
reset = 1'b0;
#(CYCLE)
load = 0;
// load mem[0] -> number of operands
@ -139,13 +115,11 @@ initial begin
for (i = 0; i < 1000; i = i + 1) begin
if (ready != 0) begin
$display("%c[32mSUCCESS: heron_top_tb tests bench finished;%c[0m", 27, 27);
displayRam();
$finish;
end
#(CYCLE) ;
end
$display("%c[31mFAILED: heron_top_tb tests timeout!%c[0m", 27, 27);
displayRam();
$finish(1);
end
endmodule