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ctrl_wires: add x_to_a_shift_1 signal

master
Jörg Thalheim 6 years ago
parent
commit
861d93d2fa
  1. 5
      cadence/heron_ctrl_wires/functional/verilog.v

5
cadence/heron_ctrl_wires/functional/verilog.v

@ -21,13 +21,14 @@ module heron_ctrl_wires (
s_to_a_shift_1,
s_to_b,
x_to_a,
x_to_a_shift_1,
x_to_b_shifted
);
input [22:0] ctrl_bus;
`define CTRL_WIRE(name,port) \
output name; \
assign name = ctrl_bus[port];
`include "heron_ctrl_wires.v"
assign name = ctrl_bus[port];
`include "heron_ctrl_wires.v"
`undef CTRL_WIRE
endmodule
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