heron_sqrt/cadence/heron_comma_fix/functional/verilog.v

module heron_comma_fix (A,Y);
  parameter comma = 8;
  parameter comma_fix = comma / 2;

  input [31:0] A;
  output [31:0] Y;
  wire [31:0] Y;

  assign Y[31: comma_fix] = A[31 - comma_fix: 0];
  assign Y[(comma_fix - 1):0] = 1'b0;
endmodule