first verilog project
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Jörg Thalheim 861d93d2fa ctrl_wires: add x_to_a_shift_1 signal 8 years ago
bericht fix formula 8 years ago
c . 9 years ago
cadence ctrl_wires: add x_to_a_shift_1 signal 8 years ago
verilog . 9 years ago
.gitignore gitignore cadence 9 years ago
Makefile Makefile: use system rsync again 8 years ago