heron_sqrt/cadence/heron_ctrl_wires/functional/verilog.v

module heron_ctrl_wires (
  ctrl_bus,
  a_to_eab,
  a_to_i,
  a_to_old_x,
  a_to_s,
  a_to_x,
  alu_mode,
  alu_res_to_a,
  alu_set_c,
  alu_set_s,
  alu_set_z,
  din_to_a,
  div_to_b_shift_1,
  edb_to_din,
  i_to_a,
  k0_to_a,
  k0_to_b,
  k1_to_b,
  old_x_to_b,
  s_to_a_shift_1,
  s_to_b,
  x_to_a,
  x_to_a_shift_1,
  x_to_b_shifted
);

  input [22:0] ctrl_bus;
  `define CTRL_WIRE(name,port) \
     output name; \
     assign name = ctrl_bus[port];
     `include "heron_ctrl_wires.v"
  `undef CTRL_WIRE
endmodule