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ctrl_wires: add x_to_a_shift_1 signal

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This commit is contained in:
Jörg Thalheim 2015-01-14 10:43:13 +01:00
parent 974a51b403
commit 861d93d2fa
1 changed files with 3 additions and 2 deletions
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5
cadence/heron_ctrl_wires/functional/verilog.v
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@ -21,13 +21,14 @@ module heron_ctrl_wires (
s_to_a_shift_1, s_to_a_shift_1,
s_to_b, s_to_b,
x_to_a, x_to_a,
x_to_a_shift_1,
x_to_b_shifted x_to_b_shifted
); );
input [22:0] ctrl_bus; input [22:0] ctrl_bus;
`define CTRL_WIRE(name,port) \ `define CTRL_WIRE(name,port) \
output name; \ output name; \
assign name = ctrl_bus[port]; assign name = ctrl_bus[port];
`include "heron_ctrl_wires.v" `include "heron_ctrl_wires.v"
`undef CTRL_WIRE `undef CTRL_WIRE
endmodule endmodule