verilog finished

verilog/heron_comma_fix.v

@@ -0,0 +1,11 @@
+module heron_comma_fix (A,Y);
+  parameter comma = 8;
+  parameter comma_fix = comma / 2;
+
+  input [31:0] A;
+  output [31:0] Y;
+  wire [31:0] Y;
+
+  assign Y[(31 - comma_fix):0] = A[(31 - comma_fix):0];
+  assign Y[31:(31 - comma_fix)] = 0;
+endmodule

verilog/heron_ctrl.v

@@ -1,33 +1,33 @@
 `include "heron_states.v"
 
 module heron_ctrl(
-  state, // ?
+  // data path
-  ready, // ?
-  ram_wr_en, // ?
-  ram_rd_en, // ?
-  alu_mode, //
-  alu_set_z, //
-  alu_set_c, //
-  alu_set_s, //
-  k0_to_b, //
-  k1_to_b, //
-  alu_res_to_a, //
   a_to_adr,
-  a_to_i, //
+  a_to_i,
-  a_to_old_x, //
+  a_to_old_x,
-  a_to_s, //
+  a_to_s,
-  a_to_x, //
+  a_to_x,
-  b_to_adr, // ?
+  alu_mode,
-  din_to_a, // ?
+  alu_res_to_a,
-  edb_to_din, // ?
+  alu_set_c,
-  a_to_do, // ?
+  alu_set_s,
-  div_to_b_shift_1, // ?
+  alu_set_z,
-  i_to_a, //
+  din_to_a,
-  old_x_to_b, //
+  div_to_b_shift_1,
-  s_to_b, //
+  edb_to_din,
-  s_to_a_shift_1, //
+  i_to_a,
-  x_to_a, //
+  k0_to_a,
-  x_to_b_shifted); // ?
+  k1_to_b,
+  old_x_to_b,
+  s_to_a_shift_1,
+  s_to_b,
+  x_to_a,
+  x_to_b_shifted,
+  // rest
+  state,
+  ready,
+  ram_rd_en,
+  ram_wr_en);
 
   // readability
   parameter ON = 1'b1;
@@ -35,103 +35,102 @@ module heron_ctrl(
   parameter MINUS = 1'b1;
   parameter PLUS = 1'b0;
 
-  input [3:0] state;
+  // data path
-
-  output ready;
-  output ram_wr_en;
-  output ram_rd_en;
-  output alu_mode;
-  output alu_set_z;
-  output alu_set_c;
-  output alu_set_s;
-  output k0_to_b;
-  output k1_to_b;
-  output alu_res_to_a;
   output a_to_adr;
   output a_to_i;
   output a_to_old_x;
   output a_to_s;
   output a_to_x;
-  output b_to_adr;
+  output alu_mode;
+  output alu_res_to_a;
+  output alu_set_c;
+  output alu_set_s;
+  output alu_set_z;
   output din_to_a;
-  output edb_to_din;
-  output a_to_do;
   output div_to_b_shift_1;
+  output edb_to_din;
   output i_to_a;
+  output k0_to_a;
+  output k1_to_b;
   output old_x_to_b;
-  output s_to_b;
   output s_to_a_shift_1;
+  output s_to_b;
   output x_to_a;
   output x_to_b_shifted;
 
-  reg ready;
+  input [3:0] state;
-  reg ram_wr_en;
+  output ready;
-  reg ram_rd_en;
+  output ram_rd_en;
-  reg rom_rd_en;
+  output ram_wr_en;
-  reg alu_mode;
+
-  reg alu_set_z;
+  // data path
-  reg alu_set_c;
-  reg alu_set_s;
-  reg k0_to_b;
-  reg k1_to_b;
-  reg alu_res_to_a;
   reg a_to_adr;
   reg a_to_i;
   reg a_to_old_x;
   reg a_to_s;
   reg a_to_x;
-  reg b_to_adr;
+  reg alu_mode;
+  reg alu_res_to_a;
+  reg alu_set_c;
+  reg alu_set_s;
+  reg alu_set_z;
   reg din_to_a;
-  reg edb_to_din;
-  reg a_to_do;
   reg div_to_b_shift_1;
+  reg edb_to_din;
   reg i_to_a;
+  reg k0_to_a;
+  reg k1_to_b;
   reg old_x_to_b;
-  reg s_to_b;
+  reg rom_rd_en;
   reg s_to_a_shift_1;
+  reg s_to_b;
   reg x_to_a;
   reg x_to_b_shifted;
 
+  reg ready;
+  reg ram_rd_en;
+  reg ram_wr_en;
+
   always @(state) begin
-    ready = OFF;
-    ram_wr_en = OFF;
-    ram_rd_en = OFF;
-    alu_mode = PLUS;
-    alu_set_z = OFF;
-    alu_set_c = OFF;
-    alu_set_s = OFF;
-    k0_to_b = OFF;
-    k1_to_b = OFF;
-    alu_res_to_a = OFF;
     a_to_adr = OFF;
     a_to_i = OFF;
     a_to_old_x = OFF;
     a_to_s = OFF;
     a_to_x = OFF;
-    b_to_adr = OFF;
+    alu_mode = PLUS;
+    alu_res_to_a = OFF;
+    alu_set_c = OFF;
+    alu_set_s = OFF;
+    alu_set_z = OFF;
     din_to_a = OFF;
-    edb_to_din = OFF;
     div_to_b_shift_1 = OFF;
+    edb_to_din = OFF;
     i_to_a = OFF;
+    k0_to_a = OFF;
+    k1_to_b = OFF;
     old_x_to_b = OFF;
-    s_to_b = OFF;
     s_to_a_shift_1 = OFF;
+    s_to_b = OFF;
     x_to_a = OFF;
     x_to_b_shifted = OFF;
 
+    ready = OFF;
+    ram_rd_en = OFF;
+    ram_wr_en = OFF;
+
     case (state)
       `IDLE: begin
         ready = ON;
       end
       `LD_N_1: begin
-        k0_to_b = ON;
+        k0_to_a = ON;
-        b_to_adr = ON;
+        a_to_adr = ON;
         edb_to_din = ON;
         ram_rd_en = ON;
       end
       `LD_N_2: begin
         din_to_a = ON;
-        k0_to_b = ON;
+        k0_to_a = ON;
         alu_mode = MINUS;
         alu_set_z = ON;
       end
@@ -183,7 +182,6 @@ module heron_ctrl(
       end
       `STORE_X: begin
         x_to_b_shifted = ON;
-        a_to_do = ON;
         ram_wr_en = ON;
       end
       `DEC_I: begin

verilog/heron_fsm.v

@@ -65,3 +65,4 @@ module heron_fsm(clk, load, reset, flag_z, flag_c, flag_s, state);
       `DEC_I: next_state = `I_GT_ZERO;
     endcase
 endmodule
+

verilog/heron_scaler64_to_32.v

@@ -0,0 +1,7 @@
+module heron_scaler64_to_32 (A,Y);
+  input [63:0] A;
+  output [31:0] Y;
+  wire [31:0] Y;
+  assign Y[30:0] = A[63:33];
+  assign Y[31] = 0;
+endmodule

verilog/heron_shift_1.v

@@ -0,0 +1,10 @@
+module heron_shift_1 (A, Y);
+
+ input [31:0] A;
+ output [31:0] Y;
+ 
+ wire [31:0] Y;
+ assign Y[30:0] = A[31:1];
+ assign Y[31] = 0;
+
+endmodule

verilog/heron_top_tb.v

@@ -0,0 +1,4 @@
+
+module heron_top_tb ( );
+
+endmodule