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861d93d2fa
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ctrl_wires: add x_to_a_shift_1 signal
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2015-01-14 10:43:13 +01:00 |
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974a51b403
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comma_fix: correct shift operation
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2015-01-14 10:42:34 +01:00 |
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4d93ceb744
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fsm: consistent spacing
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2015-01-14 10:42:14 +01:00 |
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f7ce004d4d
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Makefile: use system rsync again
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2015-01-14 10:41:44 +01:00 |
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0bc4db9639
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fix formula
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2015-01-14 10:40:58 +01:00 |
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922124b0bf
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fix loop breaker condition
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2015-01-14 10:39:45 +01:00 |
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162bb47d24
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display ram after run
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2015-01-14 10:35:53 +01:00 |
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a4d3371128
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rt_folgen: Buskonflikt behoben
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2014-01-18 12:00:17 +01:00 |
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33b786ec46
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Makefile: automating testbench
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2014-01-18 11:59:36 +01:00 |
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f3841773ab
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gitignore cadence
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2014-01-18 11:59:19 +01:00 |
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f1d6e026c8
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add cadence verilog code
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2014-01-18 11:59:04 +01:00 |
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c72c930bc0
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.
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2014-01-13 09:08:21 +01:00 |
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e664c5e777
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rt_folgen: Konstante 0 an Bus B
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2014-01-10 13:23:06 +01:00 |
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cc1f79510e
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verilog finished
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2014-01-10 13:22:11 +01:00 |
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a6e02f8e2f
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add control unit
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2014-01-08 16:35:30 +01:00 |
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1d70a432c9
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.
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2014-01-02 13:01:07 +01:00 |
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df3750364a
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correct fix-point arithmetic
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2013-12-18 10:01:06 +01:00 |
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588ee8b710
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remove unneeded limit register
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2013-12-13 10:36:19 +01:00 |
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b7399b014b
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bericht angefangen
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2013-12-11 13:57:26 +01:00 |
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1d6367161d
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.
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2013-12-06 15:11:41 +01:00 |
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86396fbadb
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.
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2013-12-04 21:32:13 +01:00 |
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b0dda9aef1
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add first Verilog example
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2013-11-11 10:27:40 +01:00 |
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7ea7968043
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first
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2013-11-11 10:26:27 +01:00 |
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